In an LCD drive IC (LDI), an off current in a chip is a matter of primary concern in driving the device in a mobile product such as a notebook, a cellular phone, etc., as opposed to a product for a desktop. A method for manufacturing a semiconductor device according to the related art will be described with reference to FIGS. 1 and 2. As shown in FIG. 1, a P type well or N type well 102 for forming a high voltage transistor is formed with a type opposite to the semiconductor substrate type 101. A plurality of trenches are formed by etching to a predetermined depth the edges of the well 102 and the semiconductor substrate 101 adjacent the well 102. After forming the well 102, a deep well may be formed by performing a deep well drive through a thermal diffusion process at a temperature of 1150° C. for 350 minutes. Next, a liner oxidation process is performed over the inner wall of the trench twice through a high-temperature thermal oxidation process.
After the high-temperature liner oxidation process, a gap-fill oxide film may be deposited over the semiconductor substrate 101 to bury the trench. A chemical mechanical polishing (CMP) process is performed to planarize the oxide film filling the trench, forming shallow trench isolation (STI) 103. Subsequently, a gate oxide film 104 and a photoresist film 105 may be formed over the semiconductor substrate 101 including the STI 103.
Next, a hard mask may be formed over the photoresist 105. The hard mask may be used for forming a low voltage well for a plurality of devices other than the transistor device shown in FIG. 1. Accordingly, as shown in FIG. 1, photoresist film 105 may be used as a mask covering the active area and the device isolating area. That is, although not shown, the mask associated with the well and the mask associated with the active area may overlap each other by 0.132 μm so that impurity ions are not implanted.
However, as shown in FIG. 2, in a semiconductor device formed according to the foregoing method, the impurity ions implanted into the high voltage well may diffuse from the boundary of the STI into the STI area. The diffusion effects may be increased by several lengthy high temperature processes during device fabrication.
The hump characteristics in the semiconductor device caused by this diffusion phenomenon are shown in a graph in FIG. 3. The current driving ability of the device may be degraded due to increased leakage current generated from the hump characteristics, which may also degrade device reliability.